Welcome to SyoSil
SyoSil is a consulting company holding broad expertise within the field of System-on-Chip and ASIC solutions, including specification, methodologies, design and verification. We are specialized in verification strategies, advanced EDA verification tools including formal methods (property checking) and EDA tool languages such as SystemVerilog.
We believe that the future for digital hardware design and verification will be using SystemVerilog. This is why we are experts in
1. RTL design using VHDL and SystemVerilog
2. Assertion based design & verification using SystemVerilog Assertions
3. Constrained random verification using SystemVerilog and the VMM/UVM methodologies
Combined with our knowledge of state-of-the-art EDA tools from major vendors, we materialize the benefits of SystemVerilog within your organization, leading to shorter design times and improved verification quality.