News

22. October. 2009 SyoSil joins partner program with CadenceSyoSil joins Cadence Verification Alliance Program (VA) read more
13. October. 2009 SyoSil live at Mentor Graphics Solutions ExpoSyoSil will be present at the European Mentor Graphics Solutions Expo, fall 2009. Visit our booth in Oulo and Espoo, Helsinki on October 13 and 15, and in Kista, Stockholm on November 11. read more
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Welcome to SyoSil
SyoSil is a consulting company holding broad expertise within the field of System-on-Chip and ASIC solutions, including specification, methodologies, design and verification. We are specialized on verification strategies, advanced EDA verification tools including formal methods (property checking) and EDA tool languages such as SystemVerilog.
We believe that the future for digital hardware design and verification will be using SystemVerilog. This is why we are experts in
1. RTL design using VHDL, Verilog95/01 and SystemVerilog
2. Assertion based design & verification using SystemVerilog Assertions
3. Object oriented test bench design using SystemVerilog Test Bench
Combined with our knowledge of state-of-the-art EDA tools from major vendors, we are capable of materializing the benefits of SystemVerilog within your organization, leading to shorter design times and improved verification quality. |
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