Publications

Papers

The VMM Performance Analyzer application provides the user with a standard mechanism for captur-ing performance data, but it provides no common usage model for enabling it inside a VMM test bench, nor how to present the captured performance results. This paper introduces a generic, uniform approach for implementing the VMM Performance Analyzer application in a VMM test bench through definition of a generic use model for enabling the application and presentation of performance results. The use model defines a set of guide lines, which allows 100% automatic generation of textual reports and graphs for the performance results.

This paper provides the reader with guidelines and advice on how to successfully deploy structural and functional coverage with VCS® 2009.12. The paper takes its offset in experiences gained from real industrial projects, and provides general solutions for several merging problems. In general, coverage is demystified through a down to Earth view on the topic. Three specific scenarios of coverage merging and mapping are presented. Each scenario addresses common misunderstandings related to coverage. Especially, when non-configurable and configurable (through parameters etc.) RTL blocks are verified in multiple testbenches and when they are instantiated multiple times in the different test benches.

This paper introduces an industry-proven, standardized way of writing VMM compliant Verification IP, namely the concept of SystemVerilog Verification Components (SVVCs). The SVVC concept standardizes how VIP offering support for both directed testing and constrained random verification is built across protocols, and offers a common look and feel. The SVVC concept offers a well documented approach of how to verify the VIP components in a stand-alone context. This approach decouples the VIP development from any RTL design development effort, and ensures that the SVVCs are fully verified before being employed in an RTL test bench. This paper also describes how VMM compliant test benches are rapidly composed based on reusing SVVCs and other generic verification components, such as scoreboards and reference models. Furthermore, on the top of such SVVC based test benches, we show how directed and constrained random test cases access the SVVCs.

Andersen, Jensen:
"Leveraging Assertion Based Verification by using Magellan"
Boston SNUG '05
RECEIVED THE "TECHNICAL COMMITTEE AWARD".
This award recognizes a paper that stands out as one that is unique, interesting and/or offers a new approach or new technology
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Design reuse of Intellectual Property (IP) is today a commonly used approach to decrease design and verification time, by using already verified design blocks in multiple chip designs. The IP reuse strategy heavily relies on standardized on-chip interfaces between IP blocks, shifting the verification problem from the block level to the system level. Verification IP (VIP) has emerged to support not only verification of protocol compliance of design blocks, but also to support system level verification of connected IP blocks from ultimately multiple vendors. As an important part of VIP, assertions describe the temporal actions on block level interfaces.
This paper describes how to employ assertions with the state-of-the-art hybrid verification tool Magellan, which comprises simulation and formal engines into an effective bug-hunter tool. Based on an existing standardized on-chip interface protocol, SystemVerilog Assertions (SVA’s) were written to constitute the VIP of that protocol. We then show how these assertions are employed with Magellan to prove the interface protocol compliance of two different design blocks attachable to the interface, without needing to write any test benches for the design blocks. This process was also a part of validating the VIP.
In this work, Magellan is primarily used to hunt bugs in existing designs - and when no more bugs can be found – formally prove that the design complies with the bus protocol. We also demonstrate how Magellan can be used to generate a stand-alone test bench for a design module, only using the assertions. This test bench environment includes a number of automatically generated constrained random test cases, yielding full assertion coverage. This test bench environment can be extracted from the Magellan setup and used as a design regression with VCS to verify that the module continuously complies with the protocol.

Ecker, Esen, Jensen, Schönberg, Steininger
"Modeling a Highly Generic Processing Unit Using SystemVerilog"
DVCon '05
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The past decades of system design have shown that generic modeling is an fficient instrument for reducing the overall design time and allows IP-reuse more easily. In this paper we describe the usage of the lately evolved hardware description and verification language (HDVL) SystemVerilog with regard to implementing a highly generic processing unit.
Our analysis shows that SystemVerilog allows writing generic designs in a more convenient manner. However it is shown that some of the useful features are still not supported by the current stage of EDA tool development. Nevertheless workarounds for the unsupported features are presented.

Jensen, Kruse, Ecker:
"SystemVerilog in Use: First RTL Synthesis Experiences with Focus on Interfaces"
European SNUG '04.
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In this paper we describe some of our experiences from bringing SystemVerilog 3.1 and DesignCompiler 2003.12 together. A number of important SystemVerilog RTL elements are discussed, and the SystemVerilog interface construct is exercised in-depth while trying to model an abstract, multiplexed bus subsystem.
The overall conclusion is that SystemVerilog together with DesignCompiler is able to leverage RTL designs from a bit and bit-vector scope to a higher abstraction level with complex data types and generic interface connections. A number of Verilog’95 pitfalls and obstructions are overcome, and the use of tool specific compiler directives is reduced. Tedious tasks such as connecting wires to instantiated module ports are minimized. Even without discussing the very rich number of minor improvements when compared to Verilog’95, SystemVerilog reveals in this paper a great modeling potential to improve the RTL design efficiency.

Jensen, Ecker, Kruse, Zambaldi:
"SystemVerilog: Interface Based Design"
FDL '04
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After establishing of various possibilities of abstraction in HDLs (on values, time, and structure) many years ago, SystemVerilog as a combined HDVL offers a new approach to support also abstraction on ports. This interface concept extends the feasibilities for encapsulation when designing, connecting, and verifying the numerous interfaces in modern SoC designs. This can be done on an abstract, non-synthesizable level but also on RT level.
The introduction of interfaces into SystemVerilog allows a more effective methodology for the implementation and verification of designs. First, an interface can be designed independently on the sub-blocks, which should be connected later. It contains not only the protocols for the transfers but also assertions derived from the specification to check all these transfers. Then, BFMs can be implemented using the interfaces and can be verified against the interface assertions. After implementation of the RTL code, this RTL code can be verified by using the BFMs and the assertions. Later, sub-designs are connected hierarchically whereby the assertion and the BFMs are used as the lowest level of the testbench hierarchy.
SystemVerilog has a lot of benefits against traditional HDLs as VHDL or Verilog and also against HVLs, as it combines many well-known concepts in a pragmatic way.

Ecker, Esen, Kruse, Steininger, Jensen:
"SVA4T: SystemVerilog Assertions - Techniques, Tips, Tricks, and Traps"
Boston SNUG '04
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ABV (Assertion Based Verification) is a very promising approach to cope with the continuously increasing verification gap. ABV works on the interface between the designer and the verification engineer. This paper gives an overview of coding and applying SVA (SystemVerilog Assertions) and gives some hints on language usage. First, a technical introduction on SVA is given in the reverse order of the LRM (i.e., starting with assertions, and then going on with properties, sequences and Boolean expressions). Next, SystemVerilog constructs and features that support the application of SVA are presented. Additionally, further SystemVerilog constructs are shown, which ease the use of SVA. They are mainly the system calls for controlling the execution of assertions and for displaying assertion messages. The next part copes with building assertions. Issues such as 'X'-handling, consideration of reset, and pipelined vs. sequential behavior is discussed. SystemVerilog implementations of the OVL, as distributed with vcs in source code are discussed nder those aspects. A set of tips and tricks resulting from our application of SVA and a set of coding rules derived from that and potentially already implemented in LEDA are shown afterwards. The paper concludes with a summary of benefits that arise from the joint design and assertion language SystemVerilog.