SyoSil will soon initiate a new project, for which we search for new team members to join our existing staff of 20 highly qualified ASIC engineers. We both look for seniors as well as newly graduated engineers.

The project will focus on digital design and verification for an RF radio ASIC, being part of a large international multi-team project. In this project, SyoSil will assume the full responsibility of several IP blocks, from architecture definition towards RTL design and coverage driven verification closure. Design and verification will be done using SystemVerilog and UVM. The project management will be SCRUM based.

We offer:

• A challenging role where you work closely with a highly skilled team as well as interfacing to engineers in leading international companies
• Access to the latest technologies and ongoing professional development, including training with ASIC tools from the top EDA vendors in the SyoSil partnership portfolio
• A competitive salary and a flexible working environment

SyoSil is a market leader in the ASIC R&D space, including RTL design/verification, device firmware and tool development. Our clients include top European and U.S. semiconductor companies working in specialized fields, such as the automotive, surveillance and telecommunication industries.

You will join a young and dynamic team of 20 engineers in a vibrant international environment close to central Copenhagen, Denmark. Contributing to large-scale project execution, you will collaborate closely with experienced and highly skilled colleagues who are all specialists within their field, giving you a unique opportunity to learn and grow.

As an ASIC/FPGA design and verification engineer, you will contribute to execution of projects on a large industrial scale, from concept and specification through RTL design to verification based on coverage closure. You will also deliver turn-key verification flows, verification IP and lead projects based on established and upcoming industry standards (SystemVerilog/UVM), helping clients improve their design and verification methodologies.

In relation to this, you can look forward to some international travel to liaise with clients and project execution.

Experience from the industry is a plus, but not essential. What matters most is that you are skilled within ASIC/FPGA design, thoroughly systematic in your work and know how to solve parallel problems simultaneously. Furthermore, you need to have good communication and presentation skills, enabling you to establish and develop strong client relations. In addition:

• You have a B.Sc. or an M.Sc. in electrical engineering or computer science, and you know how to debug complex systems in a traditional ASIC/FPGA design simulation environment.
• You have solid skills within RTL module design (Verilog/VHDL), and/or experience in verification using constrained random verification methodologies, (SystemVerilog/UVM).
• It is a strong plus if you are familiar with digital signal processing / filter design.
• It is also an advantage if you are familiar with C++ or Python and able to debug complex software systems in a traditional Linux-based software environment.
• You speak and write English fluently, and preferably Danish too.

If you recently graduated with very good results we strongly encourage you to apply for this position, as we are open towards investing in training you for the position.

Interested?

If you have any questions regarding the position, you are welcome to contact Peter Jensen at peter@syosil.com.

Please apply for the position by sending your application to Peter Jensen at peter@syosil.com.