Whole Project Outsourcing
Recently, a European telecommunications company selected SyoSil to compose an off-site project team, capable of independently executing the full ASIC/FPGA RTL design process from concept, across implementations to and including verification closure
Growing towards ten engineers, the team quickly reached critical mass, and is able to plan and execute independently, using a SCRUM based project cycle, while reporting duly to the customer.
The full project responsibility lies at SyoSil, where the group takes full responsibility for all aspects of the project, including meeting agreed deadlines. The project is expected to run across several product generations, delivering key technology from SyoSil to the telecommunications product platform.
RTL design is done using SystemVerilog and VHDL RTL, verification is done using SystemVerilog/UVM based Coverage-Metric techniques. Verification hot-spots are addressed using formal verification techniques (property checking), using SystemVerilog Assertions.
RTL design is done using SystemVerilog and VHDL RTL, verification is done using SystemVerilog/UVM based Coverage-Metric techniques. Verification hot-spots are addressed using formal verification techniques (property checking), using SystemVerilog Assertions.
As a direct result of this project, the deliveries from SyoSil enables the customer to meet critical deadlines in order to win market shares in a very fast moving market.