Employing ASIC Grade UVM Verification for FPGA Projects
This is partly due to the increased complexity, but mainly due to the fact that FPGA RTL bugs occurring in the field are not accepted in various ranges of products.
The capacity and complexity of modern FPGAs has exploded in recent years, turning the programmable circuits into valid alternatives to employing ASIC technologies. This shifts many RTL verification problems from the ASIC to the FPGA domain, but does not remove the verification challenges despite the ability to easily changing the FPGA image.
To address this issue, SyoSil sees that many companies designing products with complex FPGAs now starts using ASIC grade verification techniques such as Coverage Driven Verification using SystemVerilog/UVM.
To address this issue, SyoSil sees that many companies designing products with complex FPGAs now starts using ASIC grade verification techniques such as Coverage Driven Verification using SystemVerilog/UVM.
SyoSil stands ready to support such a process, either by executing the verification assignment on SyoSil systems employing own EDA licenses, but also through performing proper methodology training and performing lead projects at the customer sites.
FPGA verification budgets still remain limited. SyoSil specialize in implementing light versions of SystemVerilog/UVM test benches, offering all the advantages of moden Coverage Driven Verification methodologies, while keeping down the learning curve as well as the required time for obtaining verification closure of an adequate quality.
As a direct result of such engagements, SyoSil stands ready to support the introduction of SystemVerilog UVM for FPGA verification, also with the offer of executing the verification assignment on SyoSil systems using own EDA licenses.