Trusted Verification Partner for 5 Chip Generations over 10 Years
For more than a decade, SyoSil has provided ASIC design & verification services for a globally leading provider of video surveillance solutions.
Based on the customer's ASIC project life-cycles, the responsibilities for SyoSil has scaled up and down in volume, from two to seven engineers. Between projects, focus has been on improving verification methodologies, whereas the last 1-1½ year before an ASIC tape-out the SyoSil team ramps up in order to contribute to the ASIC verification closure.
Ten years is a long time, initially verification was done using SystemVerilog VMM, later UVM for which SyoSil assisted in adopting the methodology seamlessly into the customer projects.
To make this successful, SyoSil contributed by delivering key custom components to the UVM test benches and flows. The shifting SyoSil team has been self-managed by SyoSil verification specialists, ensuring a consistent and through quality was delivered to the customer project, in turn releasing the customer methodology lead engineer from the duty of supervising the work of the individual SyoSil engineer.
As a direct result of this partnership, the customer has been able to obtain and maintain a very high verification quality across 5 ASIC generations, producing first-time working silicon.